1. Technical Field
This Specification pertains generally to data communication receivers, and more specifically to recovering clock and data from a received data communication signal.
2. Related Art
In telecommunication and other data communication systems it is common to a transmit data with the associated clock embedded with the data. At the receive end, clock-data recovery (CDR) circuits extract the embedded clock information from received data, generating a recovered clock that is frequency and phase aligned to the embedded clock corresponding to the data transmission frequency. The recovered clock is then used to recover the transmitted/received data as retimed data that is frequency and phase aligned to the transmitted data.
CDR circuits commonly use a phase and frequency detector (PFD) to recover a clock aligned in frequency and phase to the embedded clock: a frequency acquisition loop includes a frequency detector (FD) that acquires a frequency close to the frequency of the embedded clock, and a phase tracking loop includes a phase detector (PD) that then phase aligns the recovered clock to the (frequency aligned) embedded clock. The recovered clock is used to generate recovered data from the received data, locked to the recovered clock which is aligned in frequency and phase to the embedded clock.
In some applications, the CDR includes a reference clock in the frequency acquisition loop, while for other applications, the CDR architecture is reference-less and only the position of the data edges is known.
Particularly (but not exclusively) for reference-less CDR designs, some mechanism for detecting an out-of-lock condition, including false lock, is advantageous. In false lock, the CDR circuit “locks” to a frequency different than the frequency of the transmitted data. In response to out-of-lock detection, the CDR can initiate a frequency/phase acquisition cycle to acquire true lock.